Job Responsibility： 岗位职责： 1. Analyze SoC architecture/specifications and translate requirements into verification items and executable plans. 分析 SoC 架构与规格文档，将需求转化为验证点和可执行计划） 2. Develop and maintain reusable UVM testbench components, including agents, sequences, scoreboards, checkers, and test case. 开发并维护可复用 UVM 验证组件，包括 agent、sequence、scoreboard、checker 及test case） 3. Create directed and constrained-random tests for core scenarios such as CPU, interconnect, DMA, interrupts, standard peripheral interfaces (UART/SPI/I2C), high-speed interfaces (PCIe/USB/Ethernet), clock/reset sequencing and error handling. 4. 针对CPU、互联、DMA、中断、标准外设接口（如UART/SPI/I2C等）、高速接口（如PCIe/USB/Ethernet等）、时钟复位时序及异常处理等核心场景开发定向和受限随机测试 5. Run simulation/regression, triage failures, debug issues with waveform and logs, and collaborate with design engineers on root-cause analysis. 执行仿真与回归，分类失败用例，结合波形与日志定位问题，并与设计工程师协同根因分析 6. Drive coverage closure through functional/code/assertion coverage analysis and targeted testcase enhancement. 通过功能/代码/断言覆盖率分析与定向补测，推进覆盖率收敛 7. Contribute to verification documentation and engineering best practices, including test plans, checklists, and reusable debug knowledge. 沉淀验证文档与工程最佳实践，包括测试计划、检查清单与可复用调试经验 Job Requirements： 任职要求： 1. Bachelor’s or Master’s degree in Microelectronics, Electronic Engineering, Computer Science, Automation, or related fields; graduating in 2027. 微电子、电子工程、计算机、自动化或相关专业本科/硕士，2027 届毕业 2. Familiarity with Verilog/SystemVerilog; exposure to UVM is a plus. 熟悉Verilog/SystemVerilog；了解UVM更佳 3. Basic understanding of on-chip protocols (AXI/AHB/APB) and register-based design concepts. 了解 AXI/AHB/APB 等片上协议及寄存器设计基础 4. Scripting skills in Python/Perl/Shell for automation and data analysis are preferred. 具备Python/Perl/Shell自动化与数据分析能力优先 5. Strong learning agility, logical thinking, communication skills, and teamwork mindset. 具备快速学习能力、逻辑分析能力、沟通能力与团队协作意识 6. Able to read English technical documentation and write clear engineering reports. 能够阅读英文技术文档并输出清晰工程报告 Job Location: Shenzhen/Shanghai/Beijing 工作地点: 深圳/上海/北京

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