Senior/Staff/Principal PCIE subsystem Design Engineer Introduction We are seeking a SOC Design Engineer specializing in PCIe Subsystems to lead the integration and optimization of high-speed interfaces for our ARM server CPUs. This role is critical for ensuring robust connectivity and peak performance for data-centric applications. Responsibilities •Responsible for integration, verification and debugging of PCIe high-speed interface IP, ensuring subsystem functionality and performance meet requirements. •Deeply understand PCIe IP configuration, register programming model, clock and reset architecture, and power management mechanisms, and lead their implementation in chip projects. •Collaborate with architecture, front-end design, backend implementation and system verification teams to jointly define the design strategy for the PCIe interface subsystem. •Lead the resolution of complex technical issues related to the PCIe subsystem throughout the entire chip development flow. •Participate in selection and evaluation of third-party PCIe IP, and conduct in-depth technical analysis and benchmarking of key modules. •Conduct key technology pre-research, prototype development and feasibility analysis for future in-house development of PCIe Controller and related modules. •Provide advanced technical support to product, test and customer support teams, and author design documents and application guides. •Track cutting-edge technology trends in PCIe and related high-speed interface protocols. Basic Qualifications •B.Sc. or above in Microelectronics, Electronic Engineering, Computer Science or related fields. •5+ years of relevant work experience in high-speed interface or SoC design. •Profound understanding of PCIe Gen5/6/7 protocol principles and implementation mechanisms; Senior/Staff/Principal CPU subsystem Design Engineer •Introduction •We are seeking a specialized CPU Subsystem Design Engineer to join our ASIC service team. In this role, you will be responsible for the architecture, integration, and delivery of the Compute Subsystem, which is the heart of our high-performance processor. •Responsibilities •Participate in requirement analysis and specification definition for the CSS. Lead the detailed architecture design and implementation of the subsystem. •Deliver the CSS design, including ARM CPU Core integration, Cache hierarchy implementation, and interconnect structure design. •Design and deliver the clock and reset schemes for the subsystem, ensuring correct clock domain partitioning and reset sequencing in multi-core scenarios. •Design and deliver low-power solutions (Per-Core Power Gating, DVFS, Clock Gating) and DFX features (Debug/Trace/MBIST/Scan). •Manage the RTL integration of the CSS, including ARM CPU Core integration, NoC access, and cache coherence protocol adaptation. •Basic Qualifications •M.Sc. or Ph.D. in Microelectronics, Electronic Engineering, or Computer Science. •5+ years of SOC design experience with a proven record of subsystem-level delivery. •Expert proficiency in Verilog/SystemVerilog RTL design and large-scale SOC subsystem integration. •Familiar with ARM CPU Core integration flows, ARM architecture, and AMBA protocols (AXI/CHI). •Solid understanding of cache coherence interconnect architecture and multi-core consistency protocols. •Experience with clock/reset design, low-power methodologies (UPF/CPF), and DFX design. •Proficient in Spyglass CDC/Lint checks and scripting languages (Python/Shell/Makefile). •Stand Out Qualifications •Experience with ARM CSS integration or CMN design. •Experience with large-scale many-core SOC design and advanced process nodes •Experience with multi-die/chiplet integration or ARM Neoverse V/N series core license integration. •Complete PCIe subsystem integration experience, familiar with pre-silicon simulation debugging and post-silicon laboratory debugging flows. •Hands-on experience with PCIe subsystem post-silicon bring-up and performance tuning for production chips. •Good cross-team communication skills and problem-solving abilities. Stand Out Qualifications •Design experience with next-generation high-speed interfaces such as CXL and UCIe. •PCIe subsystem design experience on advanced process nodes (7nm and below). •In-house development or deep customization experience of PCIe IP. •Design experience with server CPUs or high-performance computing chips. Our Culture We act with Belief—embracing uncertainty, owning challenges and driving solutions. With Solidarity, we align closely and back each other up. Staying Down-to-Earth, we drive efficiency, address customers’ real pain points and accelerate delivery. Fueled by Passion, we aim high, stay sharp, and never stop improving.

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