We are seeking a Staff/Principal PPA expert to join our CPU team. In this role, you will be responsible for CPU PPA target in generation-to-generation CPU products and support implementation issues by customers’ requests. Responsibilities Assist CPU product lead and design lead to investigate and finalize CPU PPA target on industry mainstreaming process node. Work as the contact window with platform team on implementation deliveries to achieve PPA target. Quick response for customer support on CPU PPA questions or issues. Lead the role to deliver the results to customer. Response to backend implementation from synthesis to GDSII and floorplan setup, for SoC or CPU subsystem。 Technology intelligence of process node evolution for AIoT, Embedded and Auto chips。 Qualifications B.Sc./M.Sc./Ph.D. in Microelectronics, Electrical Engineering, or related fields. 8+ years of IC backend/physical design experience Proficient in the complete SoC physical design flow, familiar with hierarchical design and large-scale chip implementation methods; capable of independently undertaking full-chip or core module backend design and completing tapeout sign-off. Skilled in mainstream industry EDA tools: ICC2, Innovus, PrimeTime, StarRC, Calibre, etc., proficient in tool parameter tuning and scenario-based customized application for complex designs. In-depth and solid understanding of STA timing analysis principles and chip power analysis theories, proficient in solving complex timing closure problems such as multi-clock domain synchronization, false path identification, timing exception handling, and high-skew clock network optimization. Solid mastery of full-flow low-power design, skilled in UPF constraint writing, power domain definition, isolation/retention strategy implementation, and capable of independently completing full-chip power analysis and low-power PPA optimization. Be familiar with DFT physical implementation flow, proficient in MBIST layout integration, scan chain placement and routing optimization, and able to resolve DFT-related timing and physical design conflicts to ensure testability and manufacturability Proficient in Tcl/Python/Shell scripting, capable of independently developing automated design scripts, optimizing batch processing flows, and improving team design efficiency. Possess strong independent problem-solving ability, project risk judgment and control capability; excellent cross-team communication and collaboration skills, able to efficiently promote project progress; proficient in reading and writing English technical documents.

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